VCS®/VCSi™ User Guide


VCS®/VCSi™ User Guide M-2017.03, March 2017 ii Copyright Notice and Proprietary Information © 2017 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Third-Party Software Notices VCS®/VCSi™ and VCS® MX/VCS® MXi™ includes or is bundled with software licensed to Synopsys under free or open-source licenses. For additional information regarding Synopsys's use of free and open-source software, refer to the third_party_notices.txt file included within the /doc directory of the installed VCS/VCS MX software. Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and to comply with them. Disclaimer SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Trademarks Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at http://www.synopsys.com/Company/Pages/Trademarks.aspx. All other product or company names may be trademarks of their respective owners. Third-Party Links Any links to third-party websites included in this document are for your convenience only. Synopsys does not endorse and is not responsible for such websites and their practices, including privacy practices, availability, and content. Synopsys, Inc. 690 E. Middlefield Road Mountain View, CA 94043 www.synopsys.com iii Contents 1. Getting Started Simulator Support with Technologies . . . . . . . . . . . . . . . . . . . . . 1-2 Simulation Preemption Support. . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Setting Up the Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Verifying Your System Configuration . . . . . . . . . . . . . . . . . . . 1-4 Obtaining a License . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Setting Up Your Environment. . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Setting Up Your C Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 SeeisUsing the Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Basic Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Default Time Unit and Time Precision . . . . . . . . . . . . . . . . . . . . . 1-9 Searching Identifiers in the Design Using UNIX Commands . . . 1-10 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 2. VCS Flow Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 iv Using vcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Commonly Used Options . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Interactive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Batch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Commonly Used Runtime Options. . . . . . . . . . . . . . . . . . . . . 2-9 3. Modeling Your Design Avoiding Race Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Using and Setting a Value at the Same Time . . . . . . . . . . . . 3-3 Setting a Value Twice at the Same Time . . . . . . . . . . . . . . . . 3-3 Flip-Flop Race Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Continuous Assignment Evaluation . . . . . . . . . . . . . . . . . . . . 3-5 Counting Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Time Zero Race Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Race Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 The Dynamic Race Detection Tool. . . . . . . . . . . . . . . . . . . . . 3-8 Introduction to the Dynamic Race Detection Tool . . . . . . 3-9 Enabling Race Detection . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 The Race Detection Report . . . . . . . . . . . . . . . . . . . . . . . 3-12 Post-Processing the Report . . . . . . . . . . . . . . . . . . . . . . . 3-15 Debugging Simulation Mismatches . . . . . . . . . . . . . . . . . 3-17 The Static Race Detection Tool . . . . . . . . . . . . . . . . . . . . . . . 3-20 Race Detection Tool to Identify Race between Clock and Data . 3-22 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 v Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 Optimizing Testbenches for Debugging. . . . . . . . . . . . . . . . . . . . 3-25 Conditional Compilation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 Enabling Debugging Features at Runtime. . . . . . . . . . . . . . . 3-28 Combining the Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 Creating Models That Simulate Faster . . . . . . . . . . . . . . . . . . . . 3-32 Unaccelerated Data Types, Primitives, and Statements . . . . 3-33 Inferring Faster Simulating Sequential Devices. . . . . . . . . . . 3-34 Modeling Faster always Blocks . . . . . . . . . . . . . . . . . . . . . . . 3-38 Using Verilog 2001 Constructs. . . . . . . . . . . . . . . . . . . . . . . . 3-39 Case Statement Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 Precedence in Text Macro Definitions . . . . . . . . . . . . . . . . . . . . . 3-42 Memory Size Limits in the Simulator . . . . . . . . . . . . . . . . . . . . . . 3-42 Using Sparse Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 Obtaining Scope Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 Scope Format Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 Returning Information About the Scope. . . . . . . . . . . . . . . . . 3-49 Avoiding Circular Dependency . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 Designing With $lsi_dumpports for Simulation and Test . . . . . . . 3-53 Dealing With Unassigned Nets . . . . . . . . . . . . . . . . . . . . . . . 3-53 Code Values at Time 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55 Cross Module Forces and No Instance Instantiation . . . . . . . 3-55 Signal Value/Strength Codes . . . . . . . . . . . . . . . . . . . . . . . . . 3-57 vi 4. Compiling the Design Compiling or Elaborating the Design in the Debug Mode . . . . . . 4-2 Compiling or Elaborating the Design in the Optimized Mode . . . 4-3 Optimizing Simulation Performance for Desired Debug Visibility With the -debug_access Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Using -debug_access to Report Global Debug Capability Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Specifying Design Regions for -debug_access Capabilities . 4-11 Enabling Additional Debug Capabilities. . . . . . . . . . . . . . . . . 4-16 Reduction in the Objects Being Dumped. . . . . . . . . . . . . . . . 4-18 Testbench Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Differences Between -debug_pp and -debug_access+pp . . . 4-19 Using -debug_access With Tab Files. . . . . . . . . . . . . . . . . . . 4-20 Using -debug_access With -ucli/-gui at Compile Time . . . . . 4-20 Unused Tab File Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 Including Tab Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 Interaction With Other Debug Options. . . . . . . . . . . . . . . . . . 4-21 Dynamic Loading of DPI Libraries at Runtime . . . . . . . . . . . . . . 4-22 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Dynamic Loading of PLI Libraries at Runtime . . . . . . . . . . . . . . . 4-24 Key Compilation or Elaboration Features . . . . . . . . . . . . . . . . . . 4-25 Initializing Verilog Variables, Registers, and Memories . . . . . 4-25 Initializing Verilog Variables, Registers, and Memories in an entire Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 vii Initializing Verilog Variables, Registers, and Memories in Selective Parts of a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 Selections for Initialization of Registers or Memories. . . . 4-31 Reporting the Initialized Values of Variables, Registers, and Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 Overriding Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32 Checking for x and z Values In Conditional Expressions. . . . 4-33 Enabling the Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35 Filtering Out False Negatives. . . . . . . . . . . . . . . . . . . . . . 4-35 Verilog Configurations and Libmaps . . . . . . . . . . . . . . . . . . . 4-37 Library Mapping Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38 Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 Hierarchical Configurations . . . . . . . . . . . . . . . . . . . . . . . 4-43 The -top Compile-Time Option . . . . . . . . . . . . . . . . . . . . . 4-44 Limitations of Configurations . . . . . . . . . . . . . . . . . . . . . . 4-44 Lint Warning Message for Missing ‘endcelldefine . . . . . . . . . 4-45 Error/Warning/Lint Message Control . . . . . . . . . . . . . . . . . . . 4-49 Controlling Error/Warning/Lint Messages Using Compile-Time Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-49 Controlling Error/Warning/Lint Messages Using a Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-66 Extracting the Files Used in Compilation . . . . . . . . . . . . . . . . 4-74 XML File Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-75 5. Simulating the Design Using DVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Using UCLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 ucli2Proc Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 viii Options for Debugging Using DVE and UCLI . . . . . . . . . . . . . . . 5-6 Reporting Forces/Injections in a Simulation . . . . . . . . . . . . . . . . 5-9 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Reporting Force/Deposit/Release Information. . . . . . . . . . . . 5-11 Handling Forces on Bit/Part Select and MDA Word. . . . . 5-12 Handling Forces on Concatenated Codes . . . . . . . . . . . . 5-13 Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Key Runtime Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 Passing Values from the Runtime Command Line . . . . . . . . 5-22 Saving and Restarting the Simulation . . . . . . . . . . . . . . . . . . 5-23 Save and Restart Example. . . . . . . . . . . . . . . . . . . . . . . . 5-24 Save and Restart File I/O . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 Save and Restart With Runtime Options . . . . . . . . . . . . . 5-26 Specifying Long Time Before Stopping the Simulation . . . . . 5-27 Preventing Time 0 Race Conditions . . . . . . . . . . . . . . . . . . . 5-29 Resolving RTL Simulation Races in Verilog Designs. . . . . . . 5-30 Recommended Approach to Resolve Race Conditions . . 5-30 Supporting Simulation Executable to Return Non-Zero Value on Error Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37 Supporting Memory Load and Dump Task Verbosity. . . . . . . 5-37 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-38 ix 6. The Unified Simulation Profiler The Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Omitting Profiling at Runtime . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Omitting the -simprofile Runtime Option . . . . . . . . . . . . . . . . 6-5 Omitting Profile Report Writing after Runtime . . . . . . . . . . . . 6-6 Specifying a Directory for the Profile Database . . . . . . . . . . . 6-7 Post Simulation Profile Information . . . . . . . . . . . . . . . . . . . . . . . 6-7 Specifying the Name of the Profile Report. . . . . . . . . . . . . . . 6-8 Running the profrpt Profile Report Generator . . . . . . . . . . . . . . . 6-8 Specifying Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 The Snapshot Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Specifying Timeline Reports . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Recording and Viewing Memory Stack Traces . . . . . . . . . . . 6-16 Reporting PLI, DPI, and DirectC Function Call Information. . 6-16 Compiling and Running the Profiler Example. . . . . . . . . . 6-17 Profiling Time Used by Various Parts of the Design. . . . . 6-18 Profiling Memory Used by Various Parts of the Design . . 6-20 The Output Directories and Files . . . . . . . . . . . . . . . . . . . . . . 6-21 The Enhanced Accumulative Views. . . . . . . . . . . . . . . . . . . . 6-22 The Comparative View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 The Caller-Callee Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 HTML Profiler Reports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 Display of Parameterized Class Functions and Tasks in Profiling Reports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-65 Hypertext Links to the Source Files . . . . . . . . . . . . . . . . . . . . 6-67 Single Text Format Report . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-70 x Stack Trace Report Example . . . . . . . . . . . . . . . . . . . . . . . . . 6-71 SystemC Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-73 Constraint Profiling Integrated in the Unified Profiler . . . . . . . . . 6-80 Changes to the Use Model for Constraint Profiling . . . . . . . . 6-81 The Time Constraint Solver View. . . . . . . . . . . . . . . . . . . . . . 6-82 The Memory Constraint Solver View . . . . . . . . . . . . . . . . . . . 6-91 Performance/Memory Profiling for Coverage Covergroups. . . . . 6-95 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-96 Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-96 HTML Profiler Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-96 Default Summary View. . . . . . . . . . . . . . . . . . . . . . . . . . . 6-97 Time/Memory Summary View . . . . . . . . . . . . . . . . . . . . . 6-97 Time/Memory Module View . . . . . . . . . . . . . . . . . . . . . . . 6-98 Time/Memory Construct View . . . . . . . . . . . . . . . . . . . . . 6-99 Time/Memory Covergroup View. . . . . . . . . . . . . . . . . . . . 6-100 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-101 Reporting Debug Capabilities for Each Module. . . . . . . . . . . . . . 6-102 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-103 HTML Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-104 Text Reports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-106 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-107 Supporting Line-Based CPU Time Profiler . . . . . . . . . . . . . . . . . 6-107 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-108 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-109 Supporting Simulation Time Slice Based Profiler . . . . . . . . . . . . 6-110 xi Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-110 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-113 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-114 Isolating the Cost of Garbage Collection. . . . . . . . . . . . . . . . . . . 6-114 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-114 Isolating the Cost of Loading Design Database . . . . . . . . . . . . . 6-115 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-115 Support for Third-Party Shared Library Profiler Report . . . . . . . . 6-116 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-117 7. Diagnostics Using Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Using –diag Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Using Smartlog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Compile-time Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Libconfig Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Timescale Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 Runtime Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 Diagnostics for VPI PLI Applications . . . . . . . . . . . . . . . . . . . 7-10 Keeping the UCLI/DVE Prompt Active After a Runtime Error 7-14 UCLI Use Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 DVE Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 UCLI Usage Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 xii Diagnosing Quickthread Issues . . . . . . . . . . . . . . . . . . . . . . . 7-20 Diagnosing Quickthread Issues in DPI. . . . . . . . . . . . . . . 7-21 Diagnosing Quickthread Issues in SystemC . . . . . . . . . . 7-22 Post-Processing Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 Using the vpdutil Utility to Generate Statistics . . . . . . . . . . . . 7-26 The vpdutil Utility Syntax . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 8. VCS Multicore Technology Application Level Parallelism Enabling Multicore Technology Application Level Parallelism. . . 8-2 Multicore SAIF File Dumping . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 9. VPD, VCD, and EVCD Utilities Advantages of VPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Dumping a VPD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Using System Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Enable and Disable Dumping. . . . . . . . . . . . . . . . . . . . . . 9-4 Override the VPD Filename . . . . . . . . . . . . . . . . . . . . . . . 9-7 Dump Multi-Dimensional Arrays and Memories. . . . . . . . 9-8 Using $vcdplusmemorydump System Task . . . . . . . . . . . 9-11 Capture Delta Cycle Information . . . . . . . . . . . . . . . . . . . 9-11 Dumping an EVCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 Using $dumpports System Task . . . . . . . . . . . . . . . . . . . . . . 9-13 Dumping EVCD File for Mixed Designs Using UCLI dump Command 9-13 xiii Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 Use Model for Dumping CCN Driver Through INOUT . . . 9-15 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 Post-processing Utilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 The vcdpost Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 Scalarizing the Vector Signals . . . . . . . . . . . . . . . . . . . . . 9-20 Uniquifying the Identifier Codes . . . . . . . . . . . . . . . . . . . . 9-21 The vcdpost Utility Syntax . . . . . . . . . . . . . . . . . . . . . . . . 9-22 The vcdiff Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23 The vcdiff Utility Output Example . . . . . . . . . . . . . . . . . . . 9-31 The vcat Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33 The vcat Utility Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34 Generating Source Files From VCD Files . . . . . . . . . . . . 9-38 Writing the Configuration File . . . . . . . . . . . . . . . . . . . . . . 9-39 The vcsplit Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43 The vcsplit Utility Syntax . . . . . . . . . . . . . . . . . . . . . . . . . 9-44 The vcd2vpd Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-47 Options for Specifying EVCD Options . . . . . . . . . . . . . . . 9-49 The vpd2vcd Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-49 The Command File Syntax. . . . . . . . . . . . . . . . . . . . . . . . 9-55 The vpdmerge Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-59 The vpdutil Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-62 10. Performance Tuning Compile-time Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 Incremental Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 xiv Compile Once and Run Many Times . . . . . . . . . . . . . . . . . . . 10-4 Parallel Compilation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Runtime Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Using Radiant Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Compiling With Radiant Technology. . . . . . . . . . . . . . . . . 10-5 Applying Radiant Technology to Parts of the Design . . . . 10-6 Improving Performance When Using PLIs. . . . . . . . . . . . . . . 10-15 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 Enabling TAB File Capabilities in UCLI Using -debug_access 10-16 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 Impact on Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-19 Obtaining VCS Consumption of CPU Resources . . . . . . . . . . . . 10-20 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 Compile Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 Simulation Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 11. Using X-Propagation Introduction to X-Propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 Guidelines for Running X-Propagation Simulations. . . . . . . . 11-4 Using the X-Propagation Simulator . . . . . . . . . . . . . . . . . . . . . . . 11-6 Specifying X-Propagation Merge Mode . . . . . . . . . . . . . . . . . 11-9 Querying X-Propagation at Runtime . . . . . . . . . . . . . . . . 11-13 X-Propagation Instrumentation Report. . . . . . . . . . . . . . . 11-14 Automatic Hardware Inference of Flip-Flops Enabled by Default 11-15 X-Propagation Configuration File. . . . . . . . . . . . . . . . . . . . . . 11-17 xv X-Propagation Configuration File Syntax . . . . . . . . . . . . . 11-18 Xprop Instrumentation Control. . . . . . . . . . . . . . . . . . . . . . . . 11-22 Process Based X-Propagation Exclusion . . . . . . . . . . . . . . . 11-25 Support for XIndex Element Merging. . . . . . . . . . . . . . . . . . . 11-25 Index BSpace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 Addressing Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 Element Merging Methods . . . . . . . . . . . . . . . . . . . . . . . . 11-29 Disabling XIndex Merging for Read or Write Operations . 11-31 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 Bounds Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 Time Zero Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39 Handling Non-pure Functions Due to Static Lifetime . . . . . . . 11-39 Supporting UCLI Commands for X-Propagation Control Tasks 11-41 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-41 UCLI Command to Specify the Merge Mode . . . . . . . . . . 11-42 UCLI Command to Control Error Messages or Warning Messages 11-43 X-Propagation Code Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 If Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 Verilog Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 Case Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 Verilog Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 Edge Sensitive Expression . . . . . . . . . . . . . . . . . . . . . . . . . . 11-47 Verilog Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-47 Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48 Verilog Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48 xvi Support for Active Drivers in X-Propagation . . . . . . . . . . . . . . . . 11-49 Combinational Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50 Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-52 Flip-flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-54 Key points to Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-56 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-57 12. Gate-Level Simulation SDF Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 Using the Unified SDF Feature . . . . . . . . . . . . . . . . . . . . . . . 12-3 Using the $sdf_annotate System Task. . . . . . . . . . . . . . . . . . 12-4 Using the -xlrm Option for SDF Retain, Gate Pulse Propagation, and Gate Pulse Detection Warning . . . . . . . . . . . . . . . . . . . . . 12-5 Using the Optimistic Mode in SDF . . . . . . . . . . . . . . . . . . 12-6 Using Gate Pulse Propagation . . . . . . . . . . . . . . . . . . . . . 12-8 Generating Warnings During Gate Pulses . . . . . . . . . . . . 12-9 Precompiling an SDF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 Creating the Precompiled Version of the SDF File. . . . . . 12-10 SDF Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 Delay Objects and Constructs . . . . . . . . . . . . . . . . . . . . . 12-13 SDF Configuration File Commands . . . . . . . . . . . . . . . . . 12-14 The INTERCONNECT_MIPD Command . . . . . . . . . . . . . 12-14 The MTM Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15 The SCALE Commands. . . . . . . . . . . . . . . . . . . . . . . . . . 12-16 An SDF Example With Configuration File . . . . . . . . . . . . 12-17 Delays and Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 Transport and Inertial Delays. . . . . . . . . . . . . . . . . . . . . . . . . 12-20 xvii The Inertial Delay Implementation . . . . . . . . . . . . . . . . . . 12-22 Enabling Transport Delays . . . . . . . . . . . . . . . . . . . . . . . . 12-23 Pulse Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24 Pulse Control With Transport Delays. . . . . . . . . . . . . . . . . . . 12-26 Pulse Control With Inertial Delays . . . . . . . . . . . . . . . . . . 12-28 Specifying Pulse on Event or Detect Behavior. . . . . . . . . 12-32 Specifying the Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37 Using the Configuration File to Disable Timing . . . . . . . . . . . . . . 12-39 Using the timopt Timing Optimizer . . . . . . . . . . . . . . . . . . . . . . . 12-40 Editing the timopt.cfg File . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42 Editing Potential Sequential Device Entries . . . . . . . . . . . 12-42 Editing Clock Signal Entries . . . . . . . . . . . . . . . . . . . . . . . 12-43 Using Scan Simulation Optimizer . . . . . . . . . . . . . . . . . . . . . . . 12-44 ScanOpt Configuration File Format . . . . . . . . . . . . . . . . . . . . 12-45 ScanOpt Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-46 Negative Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-47 The Need for Negative Value Timing Checks . . . . . . . . . . . . 12-48 The $setuphold Timing Check Extended Syntax . . . . . . . 12-53 Negative Timing Checks for Asynchronous Controls . . . . 12-56 The $recrem Timing Check Syntax . . . . . . . . . . . . . . . . . 12-57 Enabling Negative Timing Checks. . . . . . . . . . . . . . . . . . . . . 12-59 Other Timing Checks Using the Delayed Signals . . . . . . . . . 12-60 Checking Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-64 Toggling the Notifier Register. . . . . . . . . . . . . . . . . . . . . . . . . 12-65 SDF Back-Annotation to Negative Timing Checks. . . . . . . . . 12-66 How VCS Calculates Delays . . . . . . . . . . . . . . . . . . . . . . . . . 12-67 xviii 13. Coverage Code Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 Functional Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 Options For Coverage Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 14. Using OpenVera Native Testbench Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 Using Template Generator . . . . . . . . . . . . . . . . . . . . . . . . 14-5 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18 Multiple Program Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18 Configuration File Model . . . . . . . . . . . . . . . . . . . . . . . . . 14-18 Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 Usage Model for Multiple Programs. . . . . . . . . . . . . . . . . 14-20 NTB Options and the Configuration File. . . . . . . . . . . . . . 14-21 Class Dependency Source File Reordering. . . . . . . . . . . . . . 14-22 Circular Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24 Dependency-based Ordering in Encrypted Files . . . . . . . 14-25 Using Encrypted Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 Functional Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26 Using Reference Verification Methodology . . . . . . . . . . . . . . 14-26 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 xix 15. Using SystemVerilog Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 Using UVM With VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 Update on UVM-1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 Natively Compiling and Elaborating UVM-1.1d . . . . . . . . . . . 15-4 Natively Compiling and Elaborating UVM-1.2 . . . . . . . . . . . . 15-4 Compiling the External UVM Library . . . . . . . . . . . . . . . . . . . 15-5 Using the -ntb_opts uvm Option. . . . . . . . . . . . . . . . . . . . 15-5 Explicitly Specifying UVM Files and Arguments. . . . . . . . 15-6 Accessing HDL Registers Through UVM Backdoor. . . . . . . . 15-6 Generating UVM Register Abstraction Layer Code . . . . . . . . 15-7 Recording UVM Transactions . . . . . . . . . . . . . . . . . . . . . . . . 15-8 Debugging UVM Testbench Designs Using DVE. . . . . . . . . . 15-8 Recording UVM Phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 UVM Template Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 Using Mixed VMM/UVM Libraries . . . . . . . . . . . . . . . . . . . . . 15-11 Migrating from OVM to UVM . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 Where to Find UVM Examples. . . . . . . . . . . . . . . . . . . . . . . . 15-13 Where to Find UVM Documentation . . . . . . . . . . . . . . . . . . . 15-14 UVM-1.1d Documentation . . . . . . . . . . . . . . . . . . . . . . . . 15-14 UVM-VMM Interop Documentation . . . . . . . . . . . . . . . . . 15-14 Using VMM with VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 Using OVM with VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 Native Compilation and Elaboration of OVM 2.1.2 . . . . . . . . 15-15 Compiling the External OVM Library . . . . . . . . . . . . . . . . . . . 15-16 Using the -ntb_opts ovm Option. . . . . . . . . . . . . . . . . . . . 15-16 xx Explicitly Specifying OVM Files and Arguments. . . . . . . . 15-16 Recording OVM Transactions . . . . . . . . . . . . . . . . . . . . . . . . 15-17 Debugging SystemVerilog Designs . . . . . . . . . . . . . . . . . . . . . . . 15-18 Functional Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19 SystemVerilog Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19 Extern Task and Function Calls through Virtual Interfaces . . 15-21 Modport Expressions in an Interface . . . . . . . . . . . . . . . . . . . 15-24 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25 Interface Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26 Difference Between Extends and Implements . . . . . . . . . 15-29 Cast and Interface Class . . . . . . . . . . . . . . . . . . . . . . . . . 15-31 Name Conflicts and Resolution . . . . . . . . . . . . . . . . . . . . 15-32 Interface Class and Randomization . . . . . . . . . . . . . . . . . 15-36 Package Exports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-37 Severity System Tasks as Procedural Statements. . . . . . . . . 15-38 Width Casting Using Parameters. . . . . . . . . . . . . . . . . . . . . . 15-40 The std::randomize() Function. . . . . . . . . . . . . . . . . . . . . . . . 15-42 SystemVerilog Bounded Queues. . . . . . . . . . . . . . . . . . . . . . 15-45 wait() Statement with a Static Class Member Variable. . . . . . 15-46 Support for Consistent Behavior of Class Static Properties. . 15-47 Parameters and Local Parameters in Classes. . . . . . . . . . . . 15-49 SystemVerilog Math Functions . . . . . . . . . . . . . . . . . . . . . . . 15-49 Streaming Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-50 Packing (Used on RHS) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-50 Unpacking (Used on LHS) . . . . . . . . . . . . . . . . . . . . . . . . 15-51 Packing and Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . 15-51 xxi Propagation and force Statement. . . . . . . . . . . . . . . . . . . 15-52 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-52 Structures with Streaming Operators . . . . . . . . . . . . . . . . 15-52 Support for with Expression . . . . . . . . . . . . . . . . . . . . . . . 15-52 Constant Functions in Generate Blocks. . . . . . . . . . . . . . . . . 15-56 Support for Aggregate Methods in Constraints Using the “with” Construct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-57 Debugging During Initialization SystemVerilog Static Functions and Tasks in Module Definitions . . . . . . . . . . . . . . . . . . . . . . . 15-58 Explicit External Constraint Blocks . . . . . . . . . . . . . . . . . . . . 15-62 Generate Constructs in Program Blocks . . . . . . . . . . . . . . . . 15-65 Error Condition for Using a Genvar Variable Outside of its Generate Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-67 Randomizing Unpacked Structs. . . . . . . . . . . . . . . . . . . . . . . 15-68 Using the Scope Randomize Method std::randomize() . . 15-68 Using the Class Randomize Method randomize() . 15-72 Disabling and Re-enabling Randomization . . . . . . . . . . . 15-74 Using In-Line Random Variable Control. . . . . . . . . . . . . . 15-78 Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-82 Making wait fork Statements Compliant with the SV LRM. . . 15-83 Making disable fork Statements Compliant with the SV LRM 15-85 Using a Package in a SystemVerilog Module, Program, and Interface Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-87 Support for Overriding Parameter Values through Configuration 15-89 Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-89 Precedence Override Rules. . . . . . . . . . . . . . . . . . . . . . . . . . 15-90 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-90 xxii Extensions to SystemVerilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-91 Unique/Priority Case/IF Final Semantic Enhancements . . . . 15-91 Using Unique/Priority Case/If with Always Block or Continuous Assign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-92 Using Unique/Priority Inside a Function . . . . . . . . . . . . . . 15-96 System Tasks to Control Warning Messages. . . . . . . . . . 15-98 Controlling Runtime Warning Messages Generated Using Unique/ Priority If Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . 15-99 Single-Sized Packed Dimension Extension. . . . . . . . . . . . . . 15-101 Covariant Virtual Function Return Types . . . . . . . . . . . . . . . . 15-104 Self Instance of a Virtual Interface . . . . . . . . . . . . . . . . . . . . . 15-105 UVM Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-107 16. Aspect Oriented Extensions Aspect-Oriented Extensions in SystemVerilog. . . . . . . . . . . . 16-3 Processing of Aspect-Oriented Extensions as a Precompilation Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 Weaving Advice Into the Target Method. . . . . . . . . . . . . . 16-10 Precompilation Expansion Details . . . . . . . . . . . . . . . . . . . . . 16-15 Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16 17. Using Constraints Support for Array Slice in Unique Constraints. . . . . . . . . . . . . . . 17-2 Support for Object Handle Comparison in Constraint Guards. . . 17-4 Support for Pure Constraint Block. . . . . . . . . . . . . . . . . . . . . . . . 17-8 Support for SystemVerilog Bit Vector Functions in Constraints. . 17-14 $countones Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 xxiii $onehot Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17 $onehot0 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 $countbits Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20 $bits Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21 Inconsistent Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23 Constraint Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 Partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26 Randomize Serial Number. . . . . . . . . . . . . . . . . . . . . . . . . . . 17-28 Solver Trace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-28 Constraint Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-33 Test Case Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34 Using multiple +ntb_solver_debug arguments . . . . . . . . . . . 17-36 Summary for the +ntb_solver_debug Option. . . . . . . . . . . . . 17-37 +ntb_solver_debug=serial . . . . . . . . 17-37 +ntb_solver_debug=trace . . . . . . . . . 17-37 +ntb_solver_debug=profile . . . . . . . . 17-37 +ntb_solver_debug=extract . . . . . . . . 17-38 Support for Save and Restore Stimulus. . . . . . . . . . . . . . . . . 17-38 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-39 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-39 Constraint Debug Using DVE . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-40 Constraint Guard Error Suppression . . . . . . . . . . . . . . . . . . . . . . 17-42 Error Message Suppression Limitations . . . . . . . . . . . . . . . . 17-44 Flattening Nested Guard Expressions . . . . . . . . . . . . . . . 17-44 Pushing Guard Expressions into Foreach Loops. . . . . . . 17-45 xxiv Support for Array and Cross-Module References in std::randomize() 17-45 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-47 Support for Cross-Module References in Constraints. . . . . . . . . 17-48 XMR Function Calls in Constraints . . . . . . . . . . . . . . . . . . . . 17-50 State Variable Index in Constraints . . . . . . . . . . . . . . . . . . . . . . . 17-50 Runtime Check for State Versus Random Variables . . . . . . . 17-51 Array Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-52 Using DPI Function Calls in Constraints . . . . . . . . . . . . . . . . . . . 17-52 Invoking Non-pure DPI Functions from Constraints. . . . . . . . 17-53 Using Foreach Loops Over Packed Dimensions in Constraints . 17-57 Memories with Packed Dimensions. . . . . . . . . . . . . . . . . . . . 17-57 Single Packed Dimension . . . . . . . . . . . . . . . . . . . . . . . . 17-57 Multiple Packed Dimensions . . . . . . . . . . . . . . . . . . . . . . 17-58 MDAs with Packed Dimensions. . . . . . . . . . . . . . . . . . . . . . . 17-58 Single Packed Dimension . . . . . . . . . . . . . . . . . . . . . . . . 17-58 Multiple Packed Dimensions . . . . . . . . . . . . . . . . . . . . . . 17-58 Just Packed Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 17-59 The foreach Iterative Constraint for Packed Arrays. . . . . . . . 17-59 Randomized Objects in a Structure. . . . . . . . . . . . . . . . . . . . . . . 17-61 Support for Typecast in Constraints . . . . . . . . . . . . . . . . . . . . . . 17-63 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-63 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-63 Strings in Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-66 SystemVerilog LRM 1800™-2012 Update . . . . . . . . . . . . . . . . . 17-67 xxv Using Soft Constraints in SystemVerilog . . . . . . . . . . . . . . . . 17-67 Using Soft Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-68 Soft Constraint Prioritization. . . . . . . . . . . . . . . . . . . . . . . 17-69 Soft Constraints Defined in Classes Instantiated as rand Members in Another Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-70 Soft Constraints Inheritance Between Classes . . . . . . . . 17-72 Soft Constraints in AOP Extensions to a Class . . . . . . . . 17-73 Soft Constraints in View Constraints Blocks. . . . . . . . . . . 17-76 Discarding Lower-Priority Soft Constraints. . . . . . . . . . . . 17-80 Unique Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-82 Enhancement to the Randomization of Multidimensional Array Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-84 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-86 Supporting Random Array Index . . . . . . . . . . . . . . . . . . . . . . . . . 17-86 Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-87 Supporting System Function Calls . . . . . . . . . . . . . . . . . . . . . . . 17-88 $size() System Function Call . . . . . . . . . . . . . . . . . . . . . . . . . 17-88 $clog2() System Function Call. . . . . . . . . . . . . . . . . . . . . . . . 17-89 Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-89 Supporting Foreach Loop Iteration over Array Select . . . . . . . . . 17-90 18. Extensions for SystemVerilog Coverage Support for Reference Arguments in get_coverage() and get_inst_coverage() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 get_coverage() method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 get_inst_coverage() method . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 xxvi Functional Coverage Methodology Using the SystemVerilog C/C++ Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 SystemVerilog Functional Coverage Flow . . . . . . . . . . . . . . . 18-5 Covergroup Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 SystemVerilog (Covergroup for C/C++): covg.sv . . . . . . . 18-7 C Testbench: test.c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 Approach #1: Passing Arguments by Reference . . . . . . . 18-8 Approach #2: Passing Arguments by Value . . . . . . . . . . . 18-8 Compile Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 Runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 C/C++ Functional Coverage API Specification . . . . . . . . . . . 18-9 19. OpenVera-SystemVerilog Testbench Interoperability Scope of Interoperability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 Importing OpenVera Types Into SystemVerilog. . . . . . . . . . . . . . 19-3 Data Type Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 Mailboxes and Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 Enumerated Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 Integers and Bit-Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 Structs and Unions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 Connecting to the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 Mapping Modports to Virtual Ports. . . . . . . . . . . . . . . . . . . . . 19-15 Virtual Modports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16 Importing Clocking Block Members Into a Modport . . . . . 19-16 xxvii Semantic Issues With Samples, Drives, and Expects . . . . . . 19-22 Notes to Remember . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22 Blocking Functions in OpenVera . . . . . . . . . . . . . . . . . . . 19-22 Constraints and Randomization . . . . . . . . . . . . . . . . . . . 19-23 Functional Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23 Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-25 20. Using SystemVerilog Assertions Using SVAs in the HDL Design . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 Using VCS Checker Library . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 Instantiating SVA Checkers in Verilog . . . . . . . . . . . . . . . 20-3 Binding SVA to a Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 Inlining SVAs in the Verilog Design . . . . . . . . . . . . . . . . . . . . 20-5 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 Number of SystemVerilog Assertions Supported in a Module 20-7 Controlling SystemVerilog Assertions . . . . . . . . . . . . . . . . . . . . . 20-7 Compilation and Runtime Options . . . . . . . . . . . . . . . . . . . . . 20-8 Concatenating Assertion Options . . . . . . . . . . . . . . . . . . . . . 20-11 Assertion Monitoring System Tasks. . . . . . . . . . . . . . . . . . . . 20-11 Using Assertion Categories . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15 Using System Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15 Using Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 Starting and Stopping Assertions Using Assertion System Tasks 20-18 Viewing Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24 xxviii Using a Report File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24 Enhanced Reporting for SystemVerilog Assertions in Functions 20-25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-25 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-27 Name Conflict Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-27 Checker and Generate Blocks. . . . . . . . . . . . . . . . . . . . . . . . 20-27 Controlling Assertion Failure Messages . . . . . . . . . . . . . . . . . . . 20-28 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28 Options for Controlling Default Assertion Failure Messages . 20-29 Options to Control Termination of Simulation. . . . . . . . . . . . . 20-30 Option to Enable Compilation of OVA Case Pragmas. . . . . . 20-33 Reporting Values of Variables in the Assertion Failure Messages 20-34 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-35 Reporting Messages When $uniq_prior_checkon/$uniq_prior_checkoff System Tasks are Called . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-36 Assertion and Unique/Priority Re-Trigger Feature . . . . . . . . . . . 20-38 Flushing Off the Assertion Re-Trigger Feature . . . . . . . . . . . 20-40 Enabling Lint Messages for Assertions . . . . . . . . . . . . . . . . . . . . 20-41 Fail-Only Assertion Evaluation Mode . . . . . . . . . . . . . . . . . . . . . 20-44 Key Points to Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-46 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-48 Using SystemVerilog Constructs Inside vunits . . . . . . . . . . . . . . 20-49 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-49 Calling $error Task When Else Block is Not Present. . . . . . . . . . 20-50 xxix Disabling Default Assertion Success Dumping in -debug_pp Option 20-51 List of supported IEEE Std. 1800-2012 Compliant SVA Features 20-52 Support for $countbits System Function . . . . . . . . . . . . . . . . 20-55 Support for Real Data Type Variables . . . . . . . . . . . . . . . . . . 20-56 Support for $assertcontrol Assertion Control System Task . . 20-56 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-57 Enabling IEEE Std. 1800-2012 Compliant Features . . . . . . . 20-57 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-57 SystemVerilog Assertions Limitations . . . . . . . . . . . . . . . . . . . . . 20-58 Debug Support for New Constructs . . . . . . . . . . . . . . . . . 20-58 Note on Cross Features . . . . . . . . . . . . . . . . . . . . . . . . . . 20-59 21. Using Property Specification Language Including PSL in the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 Using SVA Options, SVA System Tasks, and OV Classes . . . . . 21-4 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 22. Using SystemC 23. C Language Interface Using PLI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 Writing a PLI Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 xxx Functions in a PLI Application . . . . . . . . . . . . . . . . . . . . . . . . 23-4 Header Files for PLI Applications. . . . . . . . . . . . . . . . . . . . . . 23-5 PLI Table File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 Using the PLI Table File . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22 Enabling ACC Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23 Enabling ACC Capabilities Globally . . . . . . . . . . . . . . . . . 23-23 Using the Configuration File. . . . . . . . . . . . . . . . . . . . . . . 23-24 Selected ACC Capabilities . . . . . . . . . . . . . . . . . . . . . . . . 23-28 PLI Access to Ports of Celldefine and Library Modules. . . . . 23-33 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-34 Visualization in DVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-36 Using VPI Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-36 Support for VPI Callbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-37 Support for the vpi_register_systf Routine. . . . . . . . . . . . . . . 23-38 Integrating a VPI Application With VCS. . . . . . . . . . . . . . . . . 23-39 PLI Table File for VPI Routines . . . . . . . . . . . . . . . . . . . . . . . 23-40 Virtual Interface Debug Support. . . . . . . . . . . . . . . . . . . . . . . 23-41 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-41 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-44 Unimplemented VPI Routines . . . . . . . . . . . . . . . . . . . . . . . . 23-44 Modified VPI Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-46 Backwards Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . 23-50 Diagnostics for VPI PLI Applications . . . . . . . . . . . . . . . . . . . . . . 23-50 Using DirectC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-50 Using Direct C/C++ Function Calls . . . . . . . . . . . . . . . . . . . . 23-52 Functioning of C/C++ Code in a Verilog Environment . . . 23-54 xxxi Declaring the C/C++ Function . . . . . . . . . . . . . . . . . . . . . 23-55 Calling the C/C++ Function . . . . . . . . . . . . . . . . . . . . . . . 23-62 Storing Vector Values in Machine Memory. . . . . . . . . . . . 23-63 Converting Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-66 Avoiding a Naming Problem. . . . . . . . . . . . . . . . . . . . . . . 23-69 Using Pass by Reference. . . . . . . . . . . . . . . . . . . . . . . . . 23-69 Using Direct Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-70 Using the vc_hdrs.h File. . . . . . . . . . . . . . . . . . . . . . . . . . 23-77 Access Routines for Multi-Dimensional Arrays . . . . . . . . 23-78 Using Abstract Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-80 Using vc_handle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-80 Using Access Routines . . . . . . . . . . . . . . . . . . . . . . . . . . 23-82 Summary of Access Routines . . . . . . . . . . . . . . . . . . . . . 23-125 Enabling C/C++ Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . 23-130 Mixing Direct And Abstract Access . . . . . . . . . . . . . . . . . 23-132 Specifying the DirectC.h File . . . . . . . . . . . . . . . . . . . . . . 23-132 Extended BNF for External Function Declarations . . . . . . . . 23-133 24. SAIF Support Using SAIF Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 SAIF System Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 The Flows to Generate a Backward SAIF File . . . . . . . . . . . . . . 24-5 Generating an SDPD Backward SAIF File. . . . . . . . . . . . . . . 24-5 Generating a Non-SPDP Backward SAIF File. . . . . . . . . . . . 24-6 SAIF Support for Two-Dimensional Memories in v2k Designs . . 24-7 UCLI SAIF Dumping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 xxxii Criteria for Choosing Signals for SAIF Dumping . . . . . . . . . . . . . 24-8 Improving Simulation Time by Reducing the Overhead due to SAIF File Dumping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 25. Encrypting Source Files IEEE Verilog Standard 1364-2005 Encryption. . . . . . . . . . . . . . . 25-2 The Protection Header File . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 Unsupported Protection Pragma Expressions . . . . . . . . . 25-6 Other Options for IEEE Std. 1364-2005 Encryption Mode. . . 25-7 How Protection Envelopes Work . . . . . . . . . . . . . . . . . . . . . . 25-9 The VCS Public Encryption Key . . . . . . . . . . . . . . . . . . . . . . 25-10 Creating Interoperable Digital Envelopes Using VCS - Example 25-11 Discontinued -ipkey Option . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16 128-bit Advanced Encryption Standard . . . . . . . . . . . . . . . . . . . . 25-16 Compiler Directives for Source Protection. . . . . . . . . . . . . . . 25-17 Using Compiler Directives or Pragmas . . . . . . . . . . . . . . . . . 25-17 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18 Automatic Protection Options . . . . . . . . . . . . . . . . . . . . . . . . 25-21 Using Automatic Protection Options . . . . . . . . . . . . . . . . . . . 25-24 Protecting ‘include File Directive . . . . . . . . . . . . . . . . . . . . . . 25-32 +autoincludeprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-32 Enabling Debug Access to Ports and Instance Hierarchy . . . 25-33 +autobodyprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-33 xxxiii Debugging Partially Encrypted Source Code. . . . . . . . . . . . . 25-33 Skipping Encrypted Source Code . . . . . . . . . . . . . . . . . . . . . . . . 25-34 26. Integrating VC Formal With Coverage and Planner Introduction to VC Formal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 VC Formal Coverage With Verdi Coverage and Planner . . . . . . 26-3 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3 Collecting VC Formal Results in the Coverage Database 26-3 Measuring VC Formal Assert Status in HVP . . . . . . . . . . 26-7 27. Integrating VCS With Certitude Introduction to Certitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 VCS and Certitude Integration . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 Loading Designs Automatically in Verdi with Native Certitude . . 27-4 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 Points to Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5 Dumping and Comparing Waveforms in Verdi for SystemC Designs 27-6 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 Point to Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 Reducing Compilation Time in Native Certitude With VCS Partition Compile Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-11 xxxiv 28. Integrating VCS with Vera Setting Up Vera and VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 Using Vera with VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 Usage Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 29. Integrating VCS with Specman Type Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 Usage Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 Setting Up The Environment . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 Specman e Code Accessing Verilog . . . . . . . . . . . . . . . . . . . 29-3 Using specrun and specview. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5 Adding Specman Objects To DVE. . . . . . . . . . . . . . . . . . . . . . . . 29-8 Version Checker for Specman. . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10 30. Integrating VCS with Denali Setting Up Denali Environment for VCS . . . . . . . . . . . . . . . . . . . 30-1 Integrating Denali with VCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 Use Model for Verilog Memory Models . . . . . . . . . . . . . . . . . 30-2 Execute Denali Commands at UCLI Prompt . . . . . . . . . . . . . 30-3 31. VCS and CustomSim Cosimulation Integrating VCS with CustomSim . . . . . . . . . . . . . . . . . . . . . . . . 31-1 xxxv Setting up the Environment . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 Required UNIX Paths and Variable Settings . . . . . . . . . . 31-3 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 Scheduling Analog-to-Digital Events in the NBA Region. . . . . . . 31-4 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 32. Integrating VCS with Native Low Power (NLP) 33. Unified UVM Library for VCS and Verdi Transaction/Message Recording in Verdi/DVE with VCS . . . . . . 33-4 Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4 Enabling FSDB or DVE Transaction Recording . . . . . . . . 33-4 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6 Dumping Transactions or Messages in Verdi Flow . . . . . 33-6 Dumping Transactions or Messages in DVE Flow . . . . . . 33-7 34. Integrating VCS with Verdi Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 Unified Compile Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3 Generating Verdi KDB with Unified Compile Front End. . . . . 34-3 Reading Compiled Design with Verdi. . . . . . . . . . . . . . . . 34-4 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-7 Key Points to Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-9 Dumping FSDB File for Various Flows . . . . . . . . . . . . . . . . . . . . 34-9 Setting Up Verdi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-10 xxxvi Use Model for FSDB Dumping. . . . . . . . . . . . . . . . . . . . . . . . 34-10 Using Verilog System Tasks. . . . . . . . . . . . . . . . . . . . . . . 34-11 Using UCLI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-11 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-12 Interactive and Post-Processing Debug . . . . . . . . . . . . . . . . . . . 34-13 Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-14 Interactive Simulation Debug Flow . . . . . . . . . . . . . . . . . . . . 34-15 Key Points to Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-16 Post-Processing Debug Flow. . . . . . . . . . . . . . . . . . . . . . . . . 34-16 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-17 Unified UCLI Dump Command . . . . . . . . . . . . . . . . . . . . . . . . . . 34-18 Default Dump File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-18 Default Dump Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-18 Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-19 Use Model for FSDB Dumping . . . . . . . . . . . . . . . . . . . . . 34-19 Key Points to Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-20 UCLI FSDB Dump Commands . . . . . . . . . . . . . . . . . . . . . . . 34-21 Appendix A. VCS Environment Variables Simulation Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . A-1 Optional Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . A-3 Using Environment Variables in Verilog Source Code. . . . . . . . . A-5 Appendix B. Compile-Time Options Option for Code Generation. . . . . . . . . . . . . . . . . . . . . . . . . . B-4 Options for Accessing Verilog Libraries . . . . . . . . . . . . . . . . . B-4 xxxvii Options for Incremental Compilation . . . . . . . . B-7 Options for Help. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9 Option for SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9 Options for SystemVerilog Assertions . . . . . . . . . . . . . . . . . . B-9 Options to Enable Compilation of OVA Case Pragmas . . . . . B-20 Options for Native Testbench. . . . . . . . . . . . . . . . . . . . . . . . . B-20 Options for Different Versions of Verilog . . . . . . . . . . . . . . . . B-28 Option for Initializing Verilog Variables, Registers and Memories with Random Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-30 Option for Initializing Verilog Variables, Registers and Memories in Selective Parts of a Design . . . . . . . . . . . . . . . . . . . . . . . B-33 Options for Selecting Register or Memory Initialization . . . . . B-37 Options for Using Radiant Technology. . . . . . . . . . . . . . . . . . B-38 Options for Starting Simulation Right After Compilation . . . . B-38 Options for Specifying Delays and SDF Files . . . . . . . . . . . . B-38 Options for Compiling an SDF File . . . . . . . . . . . . . . . . . . . . B-46 Options for Specify Blocks and Timing Checks . . . . . . . . . . . B-46 Options for Pulse Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . B-48 Options for Negative Timing Checks . . . . . . . . . . . . . . . . . . . B-49 Options for Profiling Your Design. . . . . . . . . . . . . . . . . . . . . . B-50 Options to Specify Source Files and Compile-time Options in a File B-50 Options for Compiling Runtime Options Into the Executable. B-53 Options for PLI Applications . . . . . . . . . . . . . . . . . . . . . . . . . B-53 Options to Enable the VCS DirectC Interface . . . . . . . . . . . . B-56 Options for Flushing Certain Output Text File Buffers . . . . . . B-57 Options for Simulating SWIFT VMC Models and SmartModels B-58 xxxviii Options for Controlling Messages . . . . . . . . . . . . . . . . . . . . . B-58 Option to Run VCS in Syntax Checking Mode. . . . . . . . . . . . B-64 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-65 Options for Cell Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . B-66 Options for Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-67 Options for Controlling the Linker . . . . . . . . . . . . . . . . . . . . . B-68 Options for Controlling the C Compiler . . . . . . . . . . . . . . . . . B-71 Options for Source Protection . . . . . . . . . . . . . . . . . . . . . . . . B-73 Options for Mixed Analog/Digital Simulation . . . . . . . . . . . . . B-73 Options for Changing Parameter Values . . . . . . . . . . . . . . . . B-75 Checking for x and z Values in Conditional Expressions. . . . B-75 Options for Detecting Race Conditions . . . . . . . . . . . . . . . . . B-76 Options to Specify the Time Scale. . . . . . . . . . . . . . . . . . . . . B-77 Option to Exclude Environment Variables During Timestamp Checks B-78 Options for Overriding Parameters . . . . . . . . . . . . . . . . . . . . B-79 Option to Enable Bounds Check at Compile-Time . . . . . . . . B-82 Option to Enable Bounds Check at Runtime . . . . . . . . . . . . . B-83 Error-[DT-OBAE] Out of Bounds Access for Queues . . . . B-84 Error-[DT-OBAE] Out of Bounds Access for Dynamic Arrays B-84 Warning-[AOOBAW] Array Out of Bounds Access for Fixed Size Unpacked Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-85 Warning-[AOOBAW] Array Out of Bounds Access for Fixed Size Packed Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-86 Error-[DT-OBAE] Intermediate Access for Dynamic Arrays B-87 Warning-[AAIIW] Array Access with Intermediate Index . B-88 Warning-[AAIIW] Array Access with Intermediate Index for Fixed Size Packed Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . B-89 xxxix General Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-89 Specifying Directories for ‘include Searches . . . . . . . . . . B-89 Enable the VCS/SystemC Cosimulation Interface . . . . . . B-90 TetraMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-91 Suppressing Port Coersion to inout . . . . . . . . . . . . . . . . . B-91 Allow Inout Port Connection Width Mismatches. . . . . . . . B-91 Allow Zero or Negative Multiconcat Multiplier . . . . . . . . . B-92 Specifying a VCD File. . . . . . . . . . . . . . . . . . . . . . . . . . . . B-92 Enabling Dumping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-92 Enabling Identifier Search . . . . . . . . . . . . . . . . . . . . . . . . B-93 Memories and Multi-Dimensional Arrays (MDAs) . . . . . . B-94 Specifying a Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-94 Changing Source File Identifiers to Upper Case . . . . . . . B-95 Defining a Text Macro. . . . . . . . . . . . . . . . . . . . . . . . . . . . B-95 Option for Macro Expansion. . . . . . . . . . . . . . . . . . . . . . . B-96 Specifying the Name of the Executable File. . . . . . . . . . . B-97 Returning The Platform Directory Name . . . . . . . . . . . . . B-97 Enabling Loop Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . B-98 Changing the Time Slot of Sequential UDP Output Evaluation B-99 Gate-Level Performance . . . . . . . . . . . . . . . . . . . . . . . . . B-99 Option to Omit Compilation of Code Between Pragmas . B-99 Generating a List of Source Files. . . . . . . . . . . . . . . . . . . B-101 Option for Dumping Environment Variables . . . . . . . . . . . B-102 Appendix C. Simulation Options Options for Simulating Native Testbenches . . . . . . . . . . . . . . C-2 Options for SystemVerilog Assertions . . . . . . . . . . . . . . . . . . C-10 Options to Control Termination of Simulation. . . . . . . . . . . . . C-20 xl Options for Enabling and Disabling Specify Blocks . . . . . . . . C-20 Options for Specifying When Simulation Stops . . . . . . . . . . . C-21 Options for Recording Output . . . . . . . . . . . . . . . . . . . . . . . . C-22 Options for Controlling Messages . . . . . . . . . . . . . . . . . . . . . C-22 Options for VPD Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-24 Options for VCD Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-26 Options for Specifying Delays . . . . . . . . . . . . . . . . . . . . . . . . C-27 Options for Flushing Certain Output Text File Buffers . . . . . . C-29 Options for Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-30 Option to Specify User-Defined Runtime Options in a File . . C-30 Option for Initializing Verilog Variables, Registers and Memories at Runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-31 Option for Initializing Verilog Variables, Registers and Memories in Selective Parts of a Design at Runtime . . . . . . . . . . . . . . C-32 General Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-34 Viewing the Compile Time Options . . . . . . . . . . . . . . . . . C-34 Recording Where ACC Capabilities are Used . . . . . . . . . C-34 Suppressing the $stop System Task . . . . . . . . . . . . . . . . C-34 Enabling User-defined Plusarg Options . . . . . . . . . . . . . . C-35 Enabling Overriding the Timing of a SWIFT SmartModel. C-35 Enabling Loop Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . C-35 Specifying acc_handle_simulated_net PLI Routine . . . . . C-36 Loading DPI Libraries Dynamically at Rutime . . . . . . . . . C-37 Loading PLI Libraries Dynamically at Runtime. . . . . . . . . C-37 Appendix D. Compiler Directives and System Tasks Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 Compiler Directives for Cell Definition . . . . . . . . . . . . . . . . . . D-2 xli Compiler Directives for Setting Defaults . . . . . . . . . . . . . . . . D-2 Compiler Directives for Macros . . . . . . . . . . . . . . . . . . . . . . . D-3 Compiler Directives for Delays. . . . . . . . . . . . . . . . . . . . . . . . D-6 Compiler Directives for Back Annotating SDF Delay Values . D-8 Compiler Directives for Source Protection. . . . . . . . . . . . . . . D-8 General Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . D-9 Compiler Directive for Including a Source File . . . . . . . . . D-9 Compiler Directive for Setting the Time Scale . . . . . . . . . D-9 Compiler Directive for Specifying a Library . . . . . . . . . . . D-10 Compiler Directive for File Names and Line Numbers . . . D-11 Unimplemented Compiler Directives . . . . . . . . . . . . . . . . . . . D-11 System Tasks and Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . D-11 System Tasks for SystemVerilog Assertions Severity . . . . . . D-11 System Tasks for SystemVerilog Assertions Control . . . . . . . D-12 System Tasks for SystemVerilog Assertions . . . . . . . . . . . . . D-13 System Tasks for VCD Files . . . . . . . . . . . . . . . . . . . . . . . . . D-14 System Tasks for LSI Certification VCD and EVCD Files . . . D-16 System Tasks for VPD Files. . . . . . . . . . . . . . . . . . . . . . . . . . D-20 System Tasks for SystemVerilog Assertions . . . . . . . . . . . . . D-27 System Tasks for Executing Operating System Commands . D-29 System Tasks for Log Files . . . . . . . . . . . . . . . . . . . . . . . . . . D-29 System Tasks for Data Type Conversions . . . . . . . . . . . . . . . D-30 System Tasks for Displaying Information. . . . . . . . . . . . . . . . D-31 System Tasks for File I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . D-31 System Tasks for Loading Memories. . . . . . . . . . . . . . . . . . . D-34 System Tasks for Time Scale. . . . . . . . . . . . . . . . . . . . . . . . . D-35 xlii System Tasks for Simulation Control . . . . . . . . . . . . . . . . . . . D-36 System Tasks for Timing Checks. . . . . . . . . . . . . . . . . . . . . . D-36 Timing Checks for Clock and Control Signals . . . . . . . . . . . . D-37 System Tasks for PLA Modeling . . . . . . . . . . . . . . . . . . . . . . D-40 System Tasks for Stochastic Analysis . . . . . . . . . . . . . . . . . . D-40 System Tasks for Simulation Time. . . . . . . . . . . . . . . . . . . . . D-41 System Tasks for Probabilistic Distribution . . . . . . . . . . . . . . D-41 System Tasks for Resetting VCS. . . . . . . . . . . . . . . . . . . . . . D-42 General System Tasks and Functions . . . . . . . . . . . . . . . . . . D-43 Checks for a Plusarg . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-43 SDF Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-43 Counting the Drivers on a Net . . . . . . . . . . . . . . . . . . . . . D-43 Depositing Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-44 Fast Processing Stimulus Patterns. . . . . . . . . . . . . . . . . . D-44 Saving and Restarting The Simulation State . . . . . . . . . . D-44 Checking for X and Z Values in Conditional Expressions D-45 Calculating Bus Widths . . . . . . . . . . . . . . . . . . . . . . . . . . D-46 Displaying the Method Stack . . . . . . . . . . . . . . . . . . . . . . D-46 IEEE Standard System Tasks Not Yet Implemented . . . . . . . D-51 Appendix E. PLI Access Routines Access Routines for Reading and Writing to Memories . . . . . . . E-2 acc_setmem_int. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-4 acc_getmem_int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5 acc_clearmem_int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-6 acc_setmem_hexstr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-11 xliii Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-12 acc_getmem_hexstr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-15 acc_setmem_bitstr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-16 acc_getmem_bitstr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-17 acc_handle_mem_by_fullname . . . . . . . . . . . . . . . . . . . . . . . E-18 acc_readmem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-18 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-19 acc_getmem_range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-21 acc_getmem_size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-22 acc_getmem_word_int. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-23 acc_getmem_word_range . . . . . . . . . . . . . . . . . . . . . . . . . . . E-24 Access Routines for Multidimensional Arrays . . . . . . . . . . . . . . . E-24 tf_mdanodeinfo and tf_imdanodeinfo. . . . . . . . . . . . . . . . . . . E-26 acc_get_mda_range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-27 acc_get_mda_word_range() . . . . . . . . . . . . . . . . . . . . . . . . . E-29 acc_getmda_bitstr() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-30 acc_setmda_bitstr() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-31 Access Routines for Probabilistic Distribution . . . . . . . . . . . . . . . E-32 vcs_random . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-33 vcs_random_const_seed. . . . . . . . . . . . . . . . . . . . . . . . . . . . E-34 vcs_random_seed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-34 vcs_dist_uniform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-35 vcs_dist_normal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-35 vcs_dist_exponential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-36 vcs_dist_poisson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-37 xliv Access Routines for Returning a Pointer to a Parameter Value . E-37 acc_fetch_paramval_str. . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-38 Access Routines for Extended VCD Files . . . . . . . . . . . . . . . . . . E-38 acc_lsi_dumpports_all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-40 acc_lsi_dumpports_call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-41 acc_lsi_dumpports_close. . . . . . . . . . . . . . . . . . . . . . . . . . . . E-43 acc_lsi_dumpports_flush . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-44 acc_lsi_dumpports_limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-45 acc_lsi_dumpports_misc . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-46 acc_lsi_dumpports_off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-47 acc_lsi_dumpports_on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-48 acc_lsi_dumpports_setformat . . . . . . . . . . . . . . . . . . . . . . . . E-50 acc_lsi_dumpports_vhdl_enable . . . . . . . . . . . . . . . . . . . . . . E-51 Access Routines for Line Callbacks . . . . . . . . . . . . . . . . . . . . . . E-52 acc_mod_lcb_add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-53 acc_mod_lcb_del. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-55 acc_mod_lcb_enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-57 acc_mod_lcb_fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-57 acc_mod_lcb_fetch2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-59 acc_mod_sfi_fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-61 Access Routines for Source Protection. . . . . . . . . . . . . . . . . . . . E-62 vcsSpClose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-66 vcsSpEncodeOff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-67 vcsSpEncodeOn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-68 vcsSpEncoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-70 xlv vcsSpGetFilePtr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-71 vcsSpInitialize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-72 vcsSpOvaDecodeLine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-73 vcsSpOvaDisable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-74 vcsSpOvaEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-75 vcsSpSetDisplayMsgFlag . . . . . . . . . . . . . . . . . . . . . . . . . . . E-77 vcsSpSetFilePtr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-77 vcsSpSetLibLicenseCode . . . . . . . . . . . . . . . . . . . . . . . . . . . E-78 vcsSpSetPliProtectionFlag. . . . . . . . . . . . . . . . . . . . . . . . . . . E-79 vcsSpWriteChar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-80 vcsSpWriteString . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-81 Access Routine for Signal in a Generate Block. . . . . . . . . . . . . . E-83 acc_object_of_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-83 VCS API Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-83 Vcsinit() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-84 VcsSimUntil() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-84 xlvi 1-1 Getting Started 1 Getting Started 1 VCS® is a high-performance, high-capacity Verilog® simulator that incorporates advanced, high-level abstraction verification technologies into a single open native platform. VCS is a compiled code simulator. It enables you to analyze, compile, and simulate Verilog, SystemVerilog, OpenVera and SystemC design descriptions. It also provides you with a set of simulation and debugging features to validate your design. These features provide capabilities for source-level debugging and simulation result viewing. VCS accelerates complete system verification by delivering the fastest and highest capacity Verilog simulation for RTL functional verification. 1-2 Getting Started This chapter includes the following sections: • “Simulator Support with Technologies” • “Simulation Preemption Support” • “Setting Up the Simulator” • “SeeisUsing the Simulator” • “Default Time Unit and Time Precision” • “Searching Identifiers in the Design Using UNIX Commands” Simulator Support with Technologies VCS supports the following IEEE standards: • The Verilog language as defined in the Standard Verilog Hardware Description Language (IEEE Std 1364). • The SystemVerilog language (with some exceptions) as defined in the IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language (IEEE Std 1800™ - 2012) In addition to its standard Verilog and SystemVerilog compilation and simulation capabilities, VCS includes the following integrated set of features and tools: • SystemC - VCS / SystemC Co-simulation Interface enables VCS and the SystemC modeling environment to work together when simulating a system described in the Verilog and SystemC languages. For more information, refer to “Using SystemC” . 1-3 Getting Started • Discovery Visualization Environment (DVE) — For more information, refer to “Using DVE” . • Unified Command-line Interface (UCLI) — For more information, refer to “Using UCLI” . • Built-In Coverage Metrics — a comprehensive built-in coverage analysis functionality that includes condition, toggle, line, finite-state-machine (FSM), path, and branch coverage. You can use coverage metrics to determine the quality of coverage of your verification test and focus on creating additional test cases. You only need to compile once to run both simulation and coverage analysis. For more information, refer to “Coverage” . • DirectC Interface — this interface allows you to directly embed user-created C/C++ functions within your Verilog design description. This results in a significant improvement in ease-of-use and performance over existing PLI-based methods. VCS atomically recognizes C/C++ function calls and integrates them for simulation, thus eliminating the need to manually create PLI files. VCS supports Synopsys DesignWare IPs, VCS Verification Library, VMC models, Vera, CustomSim, CustomSimHSIM and CustomSim FineSim. For information on integrating VCS with CustomSim, refer to the Discovery AMS: Mixed-Signal Simulation User Guide. For more information about CutomSim FineSim, see the FineSim User Guide: Pro and SPICE Reference. VCS can also be integrated with third-party tools such as Specman, Debussy, Denali, and other acceleration and emulation systems. 1-4 Getting Started Simulation Preemption Support VCS supports simulation preemption. If one suspends a VCS simulation, VCS waits for the safe memory point to suspend the job and checks in the license. When VCS simulation is resumed at a later time, it checks out the license and continues the simulation from the point where it was suspended. You can use ctrl+z or kill – TSTP to preempt simulation in VCS. Setting Up the Simulator This section outlines the basic steps for preparing to run VCS. It includes the following topics: • “Verifying Your System Configuration” • “Obtaining a License” • “Setting Up Your Environment” • “Setting Up Your C Compiler” Verifying Your System Configuration You can use the syschk.sh script to check if your system and environment match the QSC requirements for a given release of a Synopsys product. The QSC (Qualified System Configurations) represents all system configurations maintained internally and tested by Synopsys. 1-5 Getting Started To check whether the system you are on meets the QSC requirements, enter: % syschk.sh When you encounter any issue, run the script with tracing enabled to capture the output and contact Synopsys. To enable tracing, you can either uncomment the set -x line in the syschk.sh file or enter the following command: % sh -x syschk.sh >& syschk.log Use syschk.sh -v to generate a more verbose output stream including the exact path for various binaries used by the script, etc. For example: % syschk.sh -v Note: If you copy the syschk.sh script to another location before using it, you must also copy the syschk.dat data file to the same directory. You can also refer to the “Supported Platforms and Products“ section of the VCS Release Notes for the list of supported platforms, and recommended C compiler and linker versions. Obtaining a License You must have a license to run VCS. To obtain a license, contact your local Synopsys Sales Representative. Your Sales Representative will need the hostid for your machine. 1-6 Getting Started To start a new license, do the following: 1. Verify that your license file is functioning correctly: % lmcksum -c license_file_pathname Running this licensing utility ensures that the license file is not corrupt. You should see an “OK“ for every INCREMENT statement in the license file. Note: The snpslmd platform binaries and accompanying FlexLM utilities are shipped separately and are not included with this distribution. You can download these binaries as part of the Synopsys Common Licensing (SCL) kit from the Synopsys Web Site at: http://www.synopsys.com/cgi-bin/ASP/sk/smartkeys.cgi 2. Start the license server: % lmgrd -c license_file_pathname -l logfile_pathname 3. Set the LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variable to point to the license file. For example: % setenv LM_LICENSE_FILE /u/edatools/vcs/license.dat or % setenv SNPSLMD_LICENSE_FILE /u/edatools/vcs/ license.dat Note: - You can use SNPSLMD_LICENSE_FILE environment variable to set licenses explicitly for Synopsys tools. 1-7 Getting Started - If you set the SNPSLMD_LICENSE_FILE environment variable, then VCS ignores the LM_LICENSE_FILE environment variable. Setting Up Your Environment To run VCS, you need to set the following environment variables: • $VCS_HOME environment variable Set the environment variable VCS_HOME to the path where VCS is installed as shown below: % setenv VCS_HOME installation_path • $PATH environment variable Set your UNIX PATH variable to $VCS_HOME/bin as shown below: % set path = ($VCS_HOME/bin $path) OR % setenv PATH $VCS_HOME/bin:$PATH • LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE environment variable: Set the license variable LM_LICENSE_FILE or SNPSLMD_LICENSE_FILE to your license file as shown below: % setenv LM_LICENSE_FILE Location_to_the_license_file OR 1-8 Getting Started % setenv SNPSLMD_LICENSE_FILE /u/edatools/vcs/ license.dat Note: - You can use SNPSLMD_LICENSE_FILE environment variable to set licenses explicitly for Synopsys tools. - If you set the SNPSLMD_LICENSE_FILE environment variable, then VCS ignores the LM_LICENSE_FILE environment variable. For additional information on environment variables, see Appendix A, “VCS Environment Variables“. Setting Up Your C Compiler On Solaris VCS requires a C compiler to compile the intermediate files, and to link the executable file that you simulate. Solaris does not include a C compiler, therefore, you must purchase the C compiler for Solaris or use gcc. For Solaris, VCS assumes the C compiler is located in its default location (/usr/ccs/bin). RHEL32, RHEL64 and IBM RS/6000 AIX platforms all include a C compiler, and VCS assumes the compiler is located in its default location (/usr/bin). You can specify a different C compiler using the environment VCS_CC or the -cc compile-time option. SeeisUsing the Simulator VCS uses the following steps to compile and simulate Verilog designs: 1-9 Getting Started • Compiling the Design • Simulating the Design Compiling the Design VCS provides you with the vcs executable to compile and elaborate the design. This executable compiles your design using the intermediate files in the design or work library, generates the object code, and statically links them to generate a binary simulation executable, simv. For more information, see Chapter - “VCS Flow“. Simulating the Design Simulate your design by executing the binary simulation executable, simv. For more information, see Chapter - “VCS Flow“. Basic Usage Model Compilation % vcs [compile_options] Verilog_files Simulation % simv [run_options] Default Time Unit and Time Precision The default time unit is 1 s. The default time precision is 1 s. 1-10 Getting Started Searching Identifiers in the Design Using UNIX Commands You can use the following vcsfind UNIX command to search for identifiers in your design. The vcsfind script is located in $VCS_HOME/bin. You must specify the location of the fsearch.db file. vcsfind [ --] [] [(+/-)]+ Where, options Search options (see Table 1-1). These options must be separated by a “--” from the search query. Any change to the DVE GUI settings has no effect on the vcsfind command. Table 1-1 Supported Search Options Search Option Description --version Displays program's version number and exits -h, --help Displays help message and exits -b, --bw(Black and White) Highlights with bold and underline only, no colors. -d N, --dir_levels=N Prints n directory levels for every matching line. Default is 0. -f DB-FILE, --file=DB-FILE Specifies the database file. Default is vcsfind.db -H, --gui-help Prints help for GUI use. -l N, --limit=N Limits search to the first n matches. 0 means no limit. Default is 1000. 1-11 Getting Started identifier Identifier string to be searched. search group The name of the group to be included to search or excluded from search. The following search groups are supported: Packages, Modules, Ports, Parameters, Vars, Functions, Assertions, Types, Members, Instances You can also use DVE and UCLI to search for the identifiers in your design. For more information, see the Discovery Visualization Environment User Guide. -m, --match_only Matches the query pattern only. Does not display scope information. -o OUTPUT-FILE, --output=OUTPUT-FILE Outputs into a file. Default is stdout/stderr. This option bundles stdout and stderr, so -o - will redirect errors to stdout. -p, --plain Does not highlight matches in bold. -r, --regexp Regular expression search pattern. The pattern is interpreted as ^$, so .* may be desired at the beginning and end of the pattern. -t, --translate Translation mode. Prints only the translation of the query pattern into the internal SQL query string. -u, --uclimode Enables UCLI mode. This option is used for interaction with UCLI. -v, --verbose Enables verbose mode. Search Option Description 1-12 Getting Started Examples % vcsfind -f simv.daidir/debug_dump/fsearch/fsearch.db -- Top Following is the sample output: Matching modules: top.v:11 module Top scope: Top Matching instances: top.v:11 inst Top of module Top scope: Top Total: 4 results found in 0.053 seconds 2-1 VCS Flow 2 VCS Flow 1 Simulating a design using VCS involves two basic steps: • “Compilation” • “Simulation” This flow is supported only for Verilog HDL and SystemVerilog designs. For information on supported technologies, refer to “Simulator Support with Technologies” . Compilation Compiling is the first step to simulate your design. In this phase, VCS builds the instance hierarchy and generates a binary executable simv. This binary executable is later used for simulation. 2-2 VCS Flow In this phase, you can choose to compile the design either in optimized mode or in debug mode. Runtime performance of VCS is based on the mode you choose and the level of flexibility required during simulation. Synopsys recommends to use full-debug or partial-debug mode until the design correctness is achieved and then switch to optimized mode. In the optimized mode, also called as batch mode, VCS delivers the best compile time and runtime performance for a design. You typically choose optimized mode to run regressions, or when you do not require extensive debug capabilities. For more information, see “Compiling or Elaborating the Design in the Optimized Mode” . You can compile the design in debug mode, also called interactive mode, when you are in the initial phase of your development cycle, or when you need more debug capabilities or tools to debug the design issues. In this mode, the performance is not the best that VCS can deliver. However, using some of the compile time options, you can compile your design in full-debug or partial-debug mode to get maximum performance in debug mode. For more information, see “Compiling or Elaborating the Design in the Debug Mode” . Using vcs The syntax to use VCS is as follows: % vcs [compile options] Verilog_files 2-3 VCS Flow Commonly Used Options This section lists some of the commonly used vcs options. For a complete list of options, see Compilation Options. Options for Help -h or -help Lists descriptions of the most commonly used VCS compile and runtime options. -ID Returns useful information, such as VCS version and build date, VCS compiler version (same as VCS ), and your work station name, platform, and host ID (used in licensing). Options for Accessing Verilog Libraries -v filename Enables you to specify a Verilog library file. VCS looks in this file for definitions of the module and UDP instances that VCS found in your source code, however, for which it did not find the corresponding module or UDP definitions in your source code. -y directory Enables you to specify a Verilog library directory. VCS searches in the source files in this directory for definitions of the module and UDP instances that VCS found in your source code but for which it did not find the corresponding module or UDP definitions in your source code. VCS searches in this directory for a file with the same name as the module or UDP identifier in the instance (not the instance name). If it finds this file, VCS searches in the file for the module or UDP definition to resolve the instance. 2-4 VCS Flow Note: If you have multiple modules with the same name in different libraries, VCS selects the module defined in the library that is specified with the first -y option. For example: If rev1/cell.v and rev2/cell.v and rev3/cell.v all exist and define the module cell(), and you issue the following command: % vcs -y rev1 -y rev2 -y rev3 +libext+.v top.v VCS selects cell.v from rev1. However, if the top.v file has a `uselib compiler directive as follows: //top.v `uselib directory = /proj/libraries/rev3 //rest of top module code //end top.v then, `uselib takes priority. In this case, VCS uses rev3/ cell.v when you issue the following command: % vcs -y rev1 -y rev2 +libext+.v top.v Include the +libext compile time option to specify the file name extension of the files you want VCS to look for in these directories. +incdir+directory+ Specifies the directory or directories that VCS searches for include files used in the `include compiler directive. You can specify multiple directories using the plus (+) character. 2-5 VCS Flow +libext+extension+ Specifies that VCS searches only for files with the specified file name extensions in a library directory. You can specify more than one extension, separating the extensions with the plus (+) character. For example, +libext+.v+.V+ specifies searching for files with either the .v or .V extension in a library. The order in which you add file name extensions to this option does not specify an order in which VCS searches files in the library with these file name extensions. +liborder Specifies searching for module definitions for unresolved module instances through the remainder of the library where VCS finds the instance, then searching the next and then the next library on the vcs command line before searching in the first library on the command line. Note: +liborder and +librescan switches on elaboration command line will have impact only when the user specifies -y/ -v on elaboration command line. Options for 64-bit Compilation -full64 Enables compilation and simulation in 64-bit mode. Option to Specify Files and Compile Time Options in a File -file filename Specifies a file containing a list of files and compile-time options. 2-6 VCS Flow Options for Discovery Visualization Environment (DVE) and UCLI -gui When used at compile time, always starts DVE at runtime. For information on DVE, see the DVE User Guide. For information on UCLI, see the UCLI User Guide. Options for Starting Simulation After Compilation -R Runs the executable file immediately after VCS links it together. Options for Changing Parameter Values -pvalue+parameter_hierarchical_name=value Changes the specified parameter to the specified value. -parameters filename Changes parameters specified in the file to values specified in the file. The syntax for a line in the file is as follows: assign value path_to_parameter The path to the parameter is similar to a hierarchical name except that you use the forward slash character (/) instead of a period as the delimiter. Options for Controlling Messages -notice Enables verbose diagnostic messages. -q 2-7 VCS Flow Quiet mode; suppresses messages such as those about the C compiler VCS is using, the source files VCS is parsing, the top-level modules, or the specified timescale. -V Verbose mode; compiles verbosely. The compiler driver program prints the commands it executes as it runs the C compiler, assembler, and linker. Specifying a Log File -l filename Specifies a file where VCS records compilation messages. If you also enter the -R option, VCS records messages from both compilation and simulation in the same file. Defining a Text Macro +define+macro=value+ Defines a text macro in your source code to a value or character string. You can test this definition in your Verilog source code using the ‘ifdef compiler directive. Note: The =value argument is optional. For example: % vcs design.v +define+USETHIS The macro is used inside the source file using the ‘ifdef compiler directive. If this macro is not defined using the +define option, then the else portion in the code takes priority. `ifdef USETHIS 2-8 VCS Flow package p1; endpackage `else package p2; Endpackage `endif Simulation During compilation, VCS generates a binary executable, simv. You can use simv to run the simulation. Based on how you compile the design, you can run your simulation using the following modes: • Interactive mode • Batch mode For information on compiling the design, see “Compilation” . Interactive Mode You can compile your design in interactive mode, also called debug mode, in the initial phase of your design cycle. In this phase, you require abilities to debug the design issues using a GUI or through the command line. To debug using a GUI, you can use the Discovery Visualization Environment (DVE), and to debug through the command-line interface, you can use the Unified Command-line Interface (UCLI). Note: To simulate the design in the interactive mode, compile the design using the -debug, -debug_all, or -debug_access(+